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s3c921f/p921f product overview 1- 1 1 product overview sam8 8rc ri product family samsung's sam88rcri family of 8-bit single-chi p cmos microcontrollers offer fast and efficient cpu, a wide range of integrated peripherals, and supports otp device . a dual address/data bus architecture and bit- or nibble-configurable i/o ports provide a flexible programming environment for applications with varied memory and i/o requirements. timer/counters with selectable operating modes are included t o support real-time operations. s3c921f/p921f microcontroller the s3c921f can be used for dedicated control functions in a variety of applications, and is especially designed for application with voice synthesizer or etc. the s3c921f/p921f single-chip 8-bit microcontroller is fabricated using an advanced cmos process. it is built around the powerful sam88rcri cpu core. stop and idle power-down modes were implemented to reduce power consumption. to increase on-chip register space, the size of the internal register file was logically expanded. the s3c921f/p921f has 64 kbytes of program rom and 192 kbytes of data rom on-chip ( s3c921f ), and 720 bytes of ram including 16 bytes of working register and 128 bytes of lcd display ram. using the sam 88rcri design approach, the following peripherals were integrated with the sam88rcri core: ? four configurable i/o ports including ports shared with segment/common drive outputs ? 8-bit programmable pins for external interrupts ? one 8-bit basic timer for oscillation stabilization and watch-dog functions ? one 8-bit and one 16-bit timer/counter with selectable operating modes ? watch timer for real time ? two pwm modules for direct speaker drive otp the s3c921f microcontroller is also available in otp (one time programmable) version. S3P921F microcontroller has an on-chip 256 kbyte one-time-programmable eprom instead of masked rom. the S3P921F is comparable to s3c921f , both in function and in pin configuration.
product overview s3c921f/p921f 1- 2 features cpu ? sam88rcri cpu core memory ? 64k 8 bits program memory(rom) ? 192k 8 bits data memory(rom) ? 592 8 bits data memory(ram) (excluding lcd data memory) instruction set ? 41 instructions ? idle and stop instructions added for power-down modes 32 i/o pins ? i/o: 8 pins ? i/o: 24 pins(sharing with segment drive outputs) interrupts ? 15 interrupt source and 1 vector ? one interrupt level 8-bit basic timer ? watchdog timer function ? 3 kinds of clock source one 8-bit timer/counter 0 ? programmable interval timer ? external event counter function ? pwm and capture function one 16-bit timer/counter 1 ? one 16-bit timer/counter mode ? two 8-bit timer/counters a/b mode watch timer ? interval time: 3.91ms, 0.25s, 0.5s, and 1s at 32.768 khz ? 2/4/8/16 khz selectable buzzer output lcd controller/driver ? 64 segments and 16 common terminals ? 8, 12, and 16 common selectable ? internal resistor circuit for lcd bias two pwm modules ? 5/6/7/8-bits pwm selectable ? direct speaker drive ? 2-bit extendable voltage level detector ? programmable low voltage detector ? two criteria voltage(2.7 v, 4.0 v) two power-down modes ? idle: only cpu clock stops ? stop: selected system clock and cpu clock stop oscillation sources ? crystal, ceramic, or rc for main clock ? main clock frequency: 0.4 mhz - 8mhz ? 32.768 khz crystal oscillation circuit for sub clock instruction execution times ? 500ns at 8 mhz fx(minimum) operating voltage range ? 2.4 v to 5.5 v at 0.4 - 3mhz ? 2.7 v to 5.5 v at 0.4 - 4mhz ? 4.5 v to 5.5 v at 0.4 - 8mhz operating temperature range ? -40 c to +85 c package type ? 100-pin qfp package
s3c921f/p921f product overview 1- 3 block diagram p4.0/seg48- p4.7/seg55 port i/o and interrupt control sam88rcri cpu internal bus x in port 4 port 3 basic timer lcd driver/ controller reset test main osc sub osc watch timer timer 0 pwm module timer a timer b timer 1 x out xt in xt out p1.2/buz p1.3/t0ck p1.4/t0 p1.5/t1ck p1.7/tb p1.6/ta pwm0 pwm1 64-kbyte rom 592-byte register file p3.0/seg56- p3.7/seg63 voltage level detector 192-kbyte data rom port 2 port 1 p2.0/com8- p2.3/com11 p2.4/com12- p2.7/com15 p1.0/int p1.1/int p1.2/buz/int p1.3/t0ck/int p1.4/t0/int p1.5/t1ck/int p1.6/ta/int p1.7/tb/int v lc1 com0-com7 com8/p2.0- com15/p2.7 seg0-seg47 seg48/p4.0- seg55/p4.7 seg56/p3.0- seg63/p3.7 rc/ x-tal figure 1-1. block diagram
product overview s3c921f/p921f 1- 4 pin assignments seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 p4.4/seg52 p4.5/seg53 p4.6/seg54 p4.7/seg55 p3.0/seg56 p3.1/seg57 p3.2/seg58 p3.3/seg59 p3.4/seg60 p3.5/seg61 p3.6/seg62 p3.7/seg63 p2.0/com8 p2.1/com9 p2.2/com10 p2.3/com11 p2.4/com12 p2.5/com13 p2.6/com14 p2.7/com15 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 seg40 seg41 seg42 seg43 seg44 seg45 seg46 seg47 p4.0/seg48 p4.1/seg49 p4.2/seg50 p4.3/seg51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 s3c921f (100-qfp-1420c) (sdat) (sclk) seg1 seg0 com7 com6 com5 com4 com3 com2 com1 com0 v lc1 rc/ x-tal pwm0 pwm1 v dd v ss x out x in test x t in xt out reset p1.0/int p1.1/int p1.2/buz/int p1.3/t0ck/int p1.4/t0/int p1.5/t1ck/int p1.6/ta/int p1.7/tb/int figure 1-2. pin assignment (100 pin )
s3c921f/p921f product overview 1- 5 table 1- 1 . pin descriptions pin names pin type pin description circuit number pin numbers share pins p1.0, p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 i/o i/o port with bit-programmable pins; schmitt trigger input or push-pull, open- drain output and software assignable pull- ups; alternately used for external interrupt input(noise filters, interrupt enable and pending control). e-2 23, 24 25 26 27 28 29 30 int buz/int t0ck/int t0/int t1ck/int ta/int tb/int p2.0 - p2.7 i/o i/o port with nibble-programmable pins; schmitt trigger input or push-pull, open- drain output and software assignable pull- ups. h-9 38 - 31 com8- com15 p3.0 - p3.7 i/o i/o port with bit-programmable pins; schmitt trigger input or push-pull, open- drain output and software assignable pull- ups. h-8 46 - 39 seg56- seg63 p4.0 - p4.7 i/o i/o port with nibble-programmable pins; schmitt trigger input or push-pull output and software assignable pull-ups. h-10 54 - 47 seg48- seg55 pwm0 pwm1 o pwm output pins. c 13 14 ? v lc1 i lcd power supply pin. ? 11 ? int i/o external interrupt input pins. e-2 23, 24 25 26 27 28 29 30 p1.0, p1.1 p1.2/buz p1.3/t0ck p1.4/t0 p1.5/t1ck p1.6/ta p1.7/tb buz i/o output pin for buzzer signal. e-2 25 p1.2/int t0ck i/o timer 0 clock input. e-2 26 p1.3/int t0 i/o capture input or interval/pwm output. e-2 27 p1.4/int t1ck i/o timer 1/a external clock input. e-2 28 p1.5 ta i/o timer 1/a clock output. e-2 29 p1.6 tb i/o timer b clock output. e-2 30 p1.7 com0-com7 o lcd common data outputs. h-4 10 - 3 ? com8-com15 i/o lcd common data outputs. h-9 38 - 31 p2.0 - p2.7 seg0-seg47 o lcd segment data outputs. h-5 2-1 100-55 ? seg48-seg55 seg56-seg63 i/o lcd segment data outputs. h-10 h-8 54 - 47 46 - 39 p4.0 - p4.7 p3.0 - p3.7
product overview s3c921f/p921f 1- 6 table 1- 1 . pin descriptions (continued) pin names pin type pin description circuit number pin numbers share pins reset i system reset pin b 22 ? xt in ,xt out ? crystal oscillator pins for sub clock. ? 20, 21 ? x in ,x out ? main oscillator pins. ? 18, 17 ? rc/x-tal ? main oscillator type selection pin ("high" for rc osc. and "low" for x-tal) ? 12 ? test i test input: it must be connected to v ss ? 19 ? v dd ,v ss ? power input pins ? 15, 16 ?
s3c921f/p921f product overview 1- 7 pin circuit diagrams in v dd p-channel n-channel figure 1-3. pin circuit type a schmitt trigger pull-up resistor v dd pull-up resistor enable in p-channel figure 1-5. pin circuit type a-3 in v dd pull-up resistor schmitt trigger figure 1-4. pin circuit type b p-channel n-channel v dd out output disable data figure 1-6. pin circuit type c
product overview s3c921f/p921f 1- 8 n-ch v dd resistor enable v dd i/o pull-up resistor p-ch output disable data noise filter external interrupt input open-drain figure 1-7. pin circuit type e-2 i/o output disable data circuit type c resistor enable v dd pull-up resistor p-channel figure 1-8. pin circuit type e-3
s3c921f/p921f product overview 1- 9 out v ss v lc5 com data v lc1 v lc2 figure 1-9. pin circuit type h-4 out v ss v lc4 seg data v lc1 v lc3 figure 1-10. pin circuit type h-5
product overview s3c921f/p921f 1- 10 v ss v lc5 com v lc1 v lc2 output disable figure 1-11. pin circuit type h-6 out v ss v lc4 seg v lc1 v lc3 output disable figure 1-12. pin circuit type h-7
s3c921f/p921f product overview 1- 11 n-ch v dd resistor enable v dd i/o pull-up resistor p-ch data open-drain circuit type h-7 seg output disable 2 output disable 1 figure 1-13. pin circuit type h-8 n-ch v dd resistor enable v dd i/o pull-up resistor p-ch data open-drain circuit type h-6 com output disable 2 output disable 1 figure 1-14. pin circuit type h-9
product overview s3c921f/p921f 1- 12 n-ch v dd resistor enable v dd i/o pull-up resistor p-ch data circuit type h-7 seg output disable 2 output disable 1 figure 1-15. pin circuit type h-10
s3c921f/p921f elect rical data 17- 1 17 electrical data overview in this chapter, s3c921f electrical characteristics are presented in tables and graphs. the information is arranged in the following order: ? absolute maximum ratings ? d.c. electrical characteristics ? data retention supply vol tage in stop mode ? stop mode release timing when initiated by an external interrupt ? stop mode release timing when initiated by a reset ? i/o capacitance ? a.c. electrical characteristics ? input timing for external interrupts (port 1) ? input timing for reset ? oscillation characteristics ? oscillation stabilization time
electrical data s3c 921f/p921f 17- 2 table 17-1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating unit supply voltage v dd ? ? 0.3 to + 6.5 v input voltage v in ports 1, 2, 3 and 4 ? 0.3 to v dd + 0.3 v output voltage v o all output pins ? 0.3 to v dd + 0.3 v output current high i oh one i/o pin active ? 18 ma all i/o pins active ? 60 output current low i ol one i/o pin active + 30 (peak value) ma total pin current for ports 1-4 + 100 (peak value) operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 c
s3c921f/p921f elect rical data 17- 3 table 17-2. d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 2.4 v to 5.5 v) parameter symbol conditions min typ max unit operating voltage v dd fx = 8mhz (instruction clock = 2.0mhz) 4.5 ? 5.5 v fx = 4mhz (instruction clock = 1.0mhz) 2.7 ? 5.5 fx = 3mhz (instruction clock = 0.75mhz) 2.4 ? 5.5 input high voltage v ih1 ports 1-4 0.8 v dd ? v dd v v ih2 reset 0.7 v dd v dd v ih3 x in , x out and xt in v dd ? 0.1 v dd input low voltage v il1 ports 1-4 ? ? 0.2 v dd v v il2 reset 0.2 v dd v il3 x in , x out and xt in 0.1 output high voltage v oh v dd = 4.5 to 5.5 v; i oh = ?1 ma ports 1-4 v dd ? 1.0 ? ? v output low voltage v ol v dd = 4.5 to 5.5 v; i ol = 10 ma ports 1-4 ? ? 2.0 v v dd = 2.4 to 5.5 v; i ol = 1.6 ma 0.4 input high leakage current i lih1 v i = v dd ; all input pins except those specified below for i lih2 ? ? 3 a i lih2 v i = v dd ; x in , x out , xt in 20 input low leakage current i lil1 v i = 0 v; all input pins except reset , x in , x out , xt in ? ? ?3 i lil2 v i = 0 v; x in , x out , xt in ?20 output high leakage current i loh v o = v dd all output pins ? ? 3 output low leakage current i lol v o = 0 v all output pins ? ? ?3
electrical data s3c 921f/p921f 17- 4 table 17-2. d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 2.4 v to 5.5 v) parameter symbol conditions min typ max unit pull-up resistor r l1 v i = 0 v; v dd = 5v ports 1-4 25 50 75 k w v dd = 3v 50 100 150 r l2 v i = 0 v; v dd = 5v; reset 150 250 350 v dd = 3v 250 500 750 lcd voltage dividing resistor r lcd1 t a = + 25 c when lcon.1 = "0" 38 54 70 k w r lcd2 t a = + 25 c when lcon.1 = "1" 19 27 35 ? v lcd -comi ? voltage drop (i = 0-15) v dc ?15 ua per common pin ? ? 120 mv ? v lcd - seg x ? voltage drop (x = 0?63) v ds ?15 ua per common pin ? ? 120 middle output voltage (note) v lc2 v dd = 2.4 v to 5.5 v, 1/5 bias lcd clock = 0hz, v lc1 = v dd 0.8v dd ?0.2 0.8v dd 0.8v dd + 0.2 v v lc3 0.6v dd ?0.2 0.6v dd 0.6v dd + 0.2 v lc4 0.4v dd ?0.2 0.4v dd 0.4v dd + 0.2 v lc5 0.2v dd ?0.2 0.2v dd 0.2v dd + 0.2 note: i t is middle output voltage when lcd controller/driver is 1/16 duty and 1/5 bias.
s3c921f/p921f elect rical data 17- 5 table 17-2. d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 2.4 v to 5.5 v) parameter symbol conditions min typ max unit supply current (1) i dd1 (2) v dd = 5 v 10% crystal oscillator 8 mhz ? 5.0 10.0 ma c1 = c2 = 22pf 4.19 mhz 3.0 6.4 v dd = 3 v 10% 4.0 mhz 1.4 2.8 i dd2 (2) idle mode v dd = 5 v 10% 8 mhz ? 1.0 2.0 crystal oscillator c1 = c2 = 22pf 4.19 mhz 0.8 1.6 v dd = 3 v 10% 4 mhz 0.3 0.6 i dd3 (3) v dd = 3 v 10%, 32 khz crystal oscillator ? 15 30 a i dd4 (3) idle mode; v dd = 3 v 10%, 32 khz crystal oscillator ? 6 15 i dd5 stop mode; v dd =5 v 10%, osccon.2="1" ? 0.3 3 v dd =3 v 10%, 0.1 1 notes: 1. supply current does not include current drawn through internal pull-up resistors, pwm, or external output current loads. 2. i dd1 and i dd2 include power consumption for sub clock oscillation. 3. i dd3 and i dd4 are current when main clock oscillation stops and the sub clock is used. 4. every values in this table is measured when bits 4-3 of the system clock control register (clkcon.4-.3) is set to 11b.
electrical data s3c 921f/p921f 17- 6 table 17-3. data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr ? 2.2 ? 5.5 v data retention supply current i dddr stop mode, v dddr =2.2 v ? ? 1 a oscillator stabilization wait time t wait released by reset ? 2 16 /fx (1) ? ms released by interrupt ? (2) ? notes: 1. fx is the main oscillator frequency. 2. the duration of the oscillation stabilization time (t wait ) when it is released by an interrupt is determined by the setting in the basic timer control register, btcon. execution of stop instruction idle mode (basic timer active) ~ ~ v dddr ~ ~ stop mode normal operating mode data retention mode interrupt request v dd 0.8 v dd t wait figure 17-1. stop mode release timing when initiated by an external interrupt
s3c921f/p921f elect rical data 17- 7 execution of stop instrction reset occurs ~ ~ v dddr ~ ~ stop mode oscillation stabilization time normal operating mode data retention mode t wait reset v dd 0.2 v dd 0.7 v dd t srl figure 17-2. stop mode release timing when initiated by a reset reset
electrical data s3c 921f/p921f 17- 8 table 17-4. input/output capacitance (t a = ? 40 c to + 85 c, v dd = 0 v) parameter symbol conditions min typ max unit input capacitance c in f = 1 mhz; unmeasured pins are connected to v ss ? ? 10 pf output capacitance c out i/o capacitance c io table 17-5. a.c. electrical characteristics (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit interrupt input, high, low width t inth , t intl p1.0 ? p1.7 v dd = 5 v 150 200 ? ns reset input low width t rsl input v dd = 5 v 10 ? ? m s t inth t intl 0.8 v dd 0.2 v dd note: the unit t cpu means one cpu clock period. external interrupt figure 17-3. input timing for external interrupts (p1.0?p1.7) reset t rsl 0.2 v dd figure 17-4. input timing for reset reset
s3c921f/p921f elect rical data 17- 9 table 17-6. main oscillation characteristics (t a = ? 40 c + 85 c) oscillator clock configuration parameter test condition min typ max units ceramic oscillator x in c1 c2 x out oscillation frequency (1) rc/x-tal = 0 v 0.4 ? 8.0 mhz stabilization time (2) stabilization occurs when v dd is equal to the minimum oscillator voltage range. ? ? 4 ms crystal oscillator x in c1 c2 x out oscillation frequency (1) rc/x-tal = 0 v 0.4 ? 8.0 mhz stabilization time (2) v dd = 4.5 v to 5.5 v ? ? 10 ms v dd = 1.8 v to 5.5 v ? ? 30 external clock x in x out x in input frequency (1) rc/x-tal = 0 v 0.4 ? 8.0 mhz x in input high and low level width (t xh , t xl ) ? 62.0 ? 1250 ns rc oscillator x in x out r frequency (1) v dd = 2.7 v to 5.5 v rc/x-tal = v dd ? 4 ? mhz v dd = 2.4 v to 5.5 v rc/x-tal = v dd ? 2 ? notes: 1. oscillation frequency and x in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated.
electrical data s3c 921f/p921f 17- 10 t x t xl v dd -0.1 v 0.1 v x in 1/fx figure 17-5. clock timing measurement at x in
s3c921f/p921f elect rical data 17- 11 table 17-7. sub oscillation characteristics (t a = ? 40 c + 85 c, v dd = 2.4 v to 5.5 v) oscillator clock configuration parameter test condition min typ max units crystal oscillator xt in c1 c2 xt out oscillation frequency (1) ? 32 32.768 35 khz stabilization time (2) v dd = 4.5 v to 5.5 v ? 1.0 2 s v dd = 2.4 v to 4.5 v ? ? 10 external clock xt in xt out xt in input frequency (1) ? 32 ? 100 khz xt in input high and low level width (t xtl , t xth ) ? 5 ? 15 us notes: 1. oscillation frequency and xt in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillating stabilization after a power-on occurs . t xth t xtl v dd -0.1 v 0.1 v xt in 1/fxt figure 17-6. clock timing measurement at xt in
electrical data s3c 921f/p921f 17- 12 table 17-8. pwm0/pwm1 electrical characteristics ( t a = ? 40 c + 85 c) parameter symbol conditions min typ max unit pwm output voltage v pwm0 v dd = 2.4 v i pwmh0 = ?8ma v dd ? 0.5 ? ? v i pwml0 = 15 ma ? 0.5 v pwm1 v dd = 2.4 v i pwmh1 = ?12ma v dd ? 0.5 ? i pwml1 = 20 ma ? 0.5 v pwm2 v dd = 2.4 v i pwmh2 = ?16ma v dd ? 0.5 ? i pwml2 = 25 ma ? 0.5 v pwm3 v dd = 2.4 v i pwmh3 = ?20ma v dd ? 0.5 ? i pwml3 = 30 ma ? 0.5 table 17-9. vld electrical characteristics (t a = ? 40 c to + 85 c, v dd = 2.4 v to 5.5 v) parameter symbol conditions min typ max unit vld voltage v vld bldcon.4 = 0b 2.4 2.7 3.0 v bldcon.4 = 1b 3.7 4.0 4.3 vld circuit response time tb fw = 32.768 khz ? ? 1.0 ms vld operating current ibl ? 50 100 ua
s3c921f/p921f elect rical data 17- 13 2 mhz 8.32 khz 1 2 6 supply voltage (v) instruction clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16) 1.0 mhz 750 khz clock 8 mhz 4 mhz 3 mhz fx (main oscillation frequency) 400 khz 2.4 2.7 5.5 4.5 figure 17-7. operating voltage range
s3c921f/p921f mech anical data 18- 1 18 mechanical data overview the s3c921f microcontroller is currently available in a 100-pin qfp package. 100-qfp-1420c #100 20.00 0.20 23.90 0.30 14.00 0.20 17.90 0.30 0.15 + 0.10 - 0.05 0-8 0.10 max #1 0.65 note : dimensions are in millimeters. (0.58) 0.15 max 0.80 0.20 0.05 min 2.65 0.10 3.00 max 0.80 0.20 0.30 + 0.10 - 0.05 figure 19-1. 100-qfp-1420c package dimensions
s3c921f/p921f s3p92 1f otp 19- 1 19 S3P921F otp overview the S3P921F single-chip cmos microcontroller is the otp (one time programmable) version of the s3c921f microcontroller. it has an on-chip otp rom instead of a masked rom. the eprom is accessed by serial data format. the S3P921F is fully compatible with the s3c921f, both in function in d.c. electrical characteristics and in pin configuration. because of its simple programming requirements, the S3P921F is ideal as an evaluation chip for the s3c921f.
S3P921F otp s3c921f/p921 f 19- 2 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 p4.4/seg52 p4.5/seg53 p4.6/seg54 p4.7/seg55 p3.0/seg56 p3.1/seg57 p3.2/seg58 p3.3/seg59 p3.4/seg60 p3.5/seg61 p3.6/seg62 p3.7/seg63 p2.0/com8 p2.1/com9 p2.2/com10 p2.3/com11 p2.4/com12 p2.5/com13 p2.6/com14 p2.7/com15 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 seg40 seg41 seg42 seg43 seg44 seg45 seg46 seg47 p4.0/seg48 p4.1/seg49 p4.2/seg50 p4.3/seg51 seg1 seg0 com7 com6 com5 com4 com3 com2 com1 com0 v lc1 rc/ x-tal sdat /pwm0 sclk /pwm1 v dd /v dd v ss /v ss x out x in v pp /test x t in xt out reset reset /reset p1.0/int p1.1/int p1.2/buz/int p1.3/t0ck/int p1.4/t0/int p1.5/t1ck/int p1.6/ta/int p1.7/tb/int 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 S3P921F (100-qfp-1420c) figure 19-1. S3P921F pin assignments (100-pin qfp package)
s3c921f/p921f s3p92 1f otp 19- 3 table 19-1. descriptions of pins used to read/write the eprom main chip during programming pin name pin name pin no. i/o function pwm0 sdat 13 i/o serial data pin. output port when reading and input port when writing. can be assigned as a input/push-pull output port. pwm1 sclk 14 i serial clock pin. input only pin. test v pp 19 i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is applied, otp is in reading mode. (option) reset reset 22 i chip initialization v dd /v ss v dd /v ss 15/16 ? logic power supply pin. v dd should be tied to +5 v during programming. table 19-2. comparison of S3P921F and s3c921f features characteristic S3P921F s3c921f program memory 64-kbyte eprom 64-kbyte mask rom data memory 192-kbyte eprom 192-kbyte mask rom operating voltage (v dd ) 2.4 v to 5.5 v 2.4 v to 5.5 v otp programming mode v dd = 5 v, v pp (ea) = 12.5 v pin configuration 100 qfp 100 qfp eprom programmability user program 1 time programmed at the factory operating mode characteristics when 12.5 v is supplied to the v pp (ea) pin of the S3P921F, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 21-3 below. table 19-3. operating mode selection criteria v dd v pp (ea) reg/ mem mem address (a17?a0) r/w mode 5 v 5 v 0 0000h 1 eprom read 12.5 v 0 0000h 0 eprom program 12.5 v 0 0000h 1 eprom verify 12.5 v 1 0e3fh 0 eprom read protection note: "0" means low level; "1" means high level.
S3P921F otp s3c921f/p921 f 19- 4 2 mhz 8.32 khz 1 2 6 supply voltage (v) instruction clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16) 1.0 mhz 750 khz clock 8 mhz 4 mhz 3 mhz fx (main oscillation frequency) 400 khz 2.4 2.7 5.5 4.5 figure 19-2. operating voltage range

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